This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived, implemented or described. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:
BO byte offset
CPU central processing unit
DRAM dynamic random access memory
EPM energy and power management
HW hardware
LSB least significant bit
LUT look-up table
MCC multi-channel cache
MCC CTRL multi-channel cache controller
MCMC multi-channel memory controller
MMU memory management unit
PE processing element
SIMD single instructions, multiple data
SW software
TLB translation look-aside buffer
VPU vector processing unit
μP microprocessor
Processing apparatus typically comprise one or more processing units and a memory. In some cases accesses to the memory may be slower than desired. This may be due to, for example, contention between parallel accesses and/or because the memory storage used has a fundamental limit on its access speed. To alleviate this problem a cache memory may be interposed between a processing unit and the memory. The cache memory is typically smaller than the memory and may use memory storage that has a faster access speed.
Multiple processing units may be arranged with a cache available for each processing unit. Each processing unit may have its own dedicated cache. Alternatively a shared cache memory unit may comprise separate caches with the allocation of the caches between processing units determined by an integrated crossbar.